Semiconductor memory device and test method therof
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United States of America Patent
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Aug 24, 2004
Grant Date -
Apr 24, 2003
app pub date -
Jul 24, 2002
filing date -
Oct 23, 2001
priority date (Note) -
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Abstract
A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.
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