Memory and instructions in computer architecture containing processor and coprocessor
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United States of America Patent
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-
Aug 24, 2004
Grant Date -
N/A
app pub date -
May 15, 2001
filing date -
Jun 15, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions, a burst controller for executing the burst instructions, a burst instructions element for providing burst instructions in a sequence for execution by the burst controller, and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute. Burst instructions are provided by the first processor to the burst instructions element and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the data buffer in accordance with burst instructions executed by the burst controller.
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