Prioritized bus request scheduling mechanism for processing devices

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United States of America Patent

PATENT NO 6782457
APP PUB NO 20030196050A1
SERIAL NO

10454625

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Abstract

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A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bachand, Derek T Portland, OR 24 431
Hill, David L Cornelius, OR 44 1094

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