US Patent No: 6,784,020

Number of patents in Portfolio can not be more than 2000

Package structure and method for making the same

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ALSO PUBLISHED AS: 20040087043
ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MFMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ASIA PACIFIC MICROSYSTEMS, INC.HSINCHU12

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Yi-Mou Hsinchu, TW 10 30
Lee, Chengkuo Taipei, TW 11 87

Cited Art

Patent Info (Count) # Cites Year
 
GENERAL ELECTRIC COMPANY (1)
6,455,167 Coating system utilizing an oxide diffusion barrier for improved performance and repair capability 20 1999

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
TESSERA TECHNOLOGIES HUNGARY KFT. (4)
7,936,062 Wafer level chip packaging 2 2007
7,495,341 Methods and apparatus for packaging integrated circuit devices 4 2007
7,642,629 Methods and apparatus for packaging integrated circuit devices 1 2007
7,479,398 Methods and apparatus for packaging integrated circuit devices 1 2007
 
TESSERA, INC. (4)
7,566,955 High-frequency chip packages 14 2002
7,754,537 Manufacture of mountable capped chips 7 2004
8,143,095 Sequential fabrication of vertical conductive interconnects in capped chips 0 2005
7,462,932 Manufacture of mountable capped chips 6 2006
 
PRECISION MECHATRONICS PTY LTD (3)
7,380,460 Dual wafer pressure sensor 0 2007
7,464,599 Temperature compensating pressure sensor having active and reference membranes 6 2008
7,913,567 Temperature compensating pressure sensor having corrugated active membrane 0 2008
 
STATS CHIPPAC LTD. (3)
7,381,634 Integrated circuit system for bonding 1 2005
7,445,962 Stacked integrated circuits package system with dense routability and high thermal conductivity 4 2005
7,989,950 Integrated circuit packaging system having a cavity 0 2008
 
WAFER-LEVEL PACKAGING PORTFOLIO LLC (2)
7,700,397 Process for packaging components, and packaged components 0 2004
8,309,384 Process for packaging components, and packaged components 0 2010
 
ADVANCED SEMICONDUCTOR ENGINEERING, INC. (1)
8,072,081 Microelectromechanical system package 1 2008
 
BROADCOM CORPORATION (1)
8,367,475 Chip scale package assembly in reconstitution panel process format 0 2011
 
ELECTRO CERAMIC INDUSTRIES (1)
8,358,003 Surface mount electronic device packaging assembly 0 2010
 
GEORGIA TECH RESEARCH CORPORATION (1)
8,335,084 Embedded actives and discrete passives in a cavity within build-up layers 0 2006
 
GLOBALFOUNDRIES INC. (1)
8,144,478 Circuit module and method 0 2005
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
7,436,683 Wafer level packaging structure with inductors and manufacture method thereof 3 2006
 
MICRON TECHNOLOGY, INC. (1)
8,258,006 Method for fabricating stacked semiconductor components 0 2008
 
NORTHROP GRUMMAN SYSTEMS CORPORATION (1)
6,939,784 Wafer scale package and method of assembly 4 2004
 
OPTOPAC, INC. (1)
7,291,518 Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof 2 2005
 
SANDIA CORPORATION (1)
7,335,972 Heterogeneously integrated microsystem-on-a-chip 52 2003
 
STMICROELECTRONICS ASIA PACIFIC PTE LTD-SINGAPORE (1)
8,164,179 Chip scale package structure with can attachment 0 2008
 
STMICROELECTRONICS ASIA PACIFIC PTE LTD. (1)
8,389,335 Chip Scale Package structure with can attachment 0 2012
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
8,035,984 Substrate structures and methods for electronic circuits 0 2009

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Feb 29, 2016
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00