Adaptive variable frequency clock system for high performance low power microprocessors
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United States of America Patent
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Sep 7, 2004
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N/A
app pub date -
Jun 6, 2003
filing date -
Oct 22, 2001
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Abstract
A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
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