Asynchronous, high-bandwidth memory component using calibrated timing elements
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United States of America Patent
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Sep 7, 2004
Grant Date -
Feb 27, 2003
app pub date -
Oct 15, 2002
filing date -
Feb 28, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
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