Method and apparatus for vector processing
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United States of America Patent
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Sep 7, 2004
Grant Date -
N/A
app pub date -
May 3, 2001
filing date -
May 3, 2001
priority date (Note) -
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Abstract
A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift register is used to perform a first vector space reduction, and the MISR is used to perform a second vector space compression. Accordingly the MISR may be scaled down in input width by a reduction factor of the shift register.
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