Clock controlling method and circuit with a multi-phase multiplication clock generating circuit
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United States of America Patent
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Sep 14, 2004
Issued Date -
N/A
app pub date -
Feb 20, 2003
filing date -
Jul 21, 2000
priority date (Note) -
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Abstract
A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.
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