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Abstract

A bit synchronizer for a digital receiver system accounts for loss of bit synchronization due to transmission phenomena. The bit synchronizer includes a DC level estimator for converting a sampled digital signal having a bit rate and a sampling rate into a level-adjusted signal. A delay module generates a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The timing signals correspond to early, on-time, and late sampling windows. The control module generates an output signal based on the timing signals such that the transmit and receive bit timing are synchronized. In one embodiment, the control module has an absolute value stage, an integration stage, and a signal selector. The signal selector is able to select between the timing signals, adjust the symbol rate to re-center the on-time gate, and memory swap to maintain correct averaging operations.

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First Claim