Memory system with burst length shorter than prefetch length
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 21, 2004
Grant Date -
Sep 25, 2003
app pub date -
Mar 22, 2002
filing date -
Mar 22, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully