Method and apparatus for instruction execution in a data processing system
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United States of America Patent
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Sep 21, 2004
Issued Date -
N/A
app pub date -
Jun 12, 2000
filing date -
Feb 16, 2000
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Abstract
A method for processing scalar and vector executions, where vector executions may be 'true' vector operations, CVA, or pseudo-vector operations, PVA. All three types of executions are processed using one architecture. In one embodiment, a compiler analyzes code to identify sections that are vectorizable, and applies either CVA, PVA, or a combination of the two to process these sections. Register overlay is provided for storing load address information and data in PVA mode. Within each CVA and PVA instruction, enable bits describe the data streaming function of the operation. A temporary memory, TM, accommodates variable size vectors, and is used in vector operations, similar to a vector register, to store temporary vectors.
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