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Abstract

A method is presented for built-in redundancy analysis of a semiconductor memory device. The method does not require retention of an entire memory bitmap, and may be implemented on-chip and integrated within existing BIST circuitry. The regular memory is comprehensively tested, and defective rows and columns are flagged for replacement by redundant rows and/or columns; the elements containing the most defects are the first to be flagged. If all of the defective memory locations can be replaced using redundant rows and columns, the method designates the memory as repairable; a repair solution may then be scanned out of the memory device. The method is believed to provide a fast, cost-effective means of testing and repairing memory devices, with a consequent improvement in production yields.

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First Claim