Technique for suppression of edge current in semiconductor devices
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United States of America Patent
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Sep 28, 2004
Grant Date -
Dec 12, 2002
app pub date -
Aug 7, 2002
filing date -
Apr 20, 2000
priority date (Note) -
Expired
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Abstract
A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| DIGLRAD CORPORATION | POWAY CA |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Carlson, Lars S | Del Mar, CA | 19 | 595 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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