Packet prioritization processing technique for routing traffic in a packet-switched computer network

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United States of America Patent

PATENT NO 6798743
SERIAL NO

09274091

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Abstract

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A two-phase packet processing technique is provided for routing traffic in a packet-switched, integrated services network which supports a plurality of different service classes. During Phase I, packets are retrieved from the router input interface and classified in order to identify the associated priority level of each packet and/or to determine whether a particular packet is delay-sensitive. If it is determined that a particular packet is delay-sensitive, the packet is immediately and fully processed. If, however, it is determined that the packet is not delay-sensitive, full processing of the packet is deferred and the packet is stored in an intermediate data structure. During Phase II, packets stored within the intermediate data structure are retrieved and fully processes. The technique of the present invention significantly reduces packet processing latency, particularly with respect to high priority or delay-sensitive packets. It is easily implemented in conventional routing systems, imposes little computational overhead, and consumes only a limited amount of memory resources within such systems.

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Patent Owner(s)

Patent OwnerAddress
CISCO TECHNOLOGY INC170 WEST TASMAN DRIVE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Agasaveeran, Saravanan Sunnyvale, CA 10 581
Berl, Steven Piedmont, CA 5 389
Ma, Qingming Santa Clara, CA 45 2440
Shi, Zhanhe San Jose, CA 12 495

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