MEMORY ARCHITECTURE WITH SERIES GROUPED BY CELLS
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United States of America Patent
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Oct 5, 2004
Grant Date -
Nov 25, 2004
app pub date -
Dec 30, 2002
filing date -
Dec 30, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two,or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.
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