System, circuit and method for low voltage operable, small footprint delay
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United States of America Patent
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Oct 5, 2004
Grant Date -
Dec 25, 2003
app pub date -
Jun 25, 2002
filing date -
Jun 25, 2002
priority date (Note) -
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Abstract
The present invention is a system, circuit and method for low voltage operable, small footprint delay. The delay circuit of the present invention uses an input switching configuration with a limited gate to source conductance to enhance the delay time for any given resistor and capacitor area in an RC network. According to the delay circuit of the present invention, the output of the RC network transitions very slowly in order to achieve a long delay. When the next stage of the delay circuit trips, the limited gate to source conductance is bypassed to allow rapid full rail presetting or resetting on the output of the RC network. This rapid full rail presetting or resetting limits power consumption and rapidly prepares the delay circuit for the next edge transition or cycle. Methods and systems incorporating the delay circuit and techniques of the present invention are also disclosed.
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