Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith
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United States of America Patent
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Oct 5, 2004
Grant Date -
N/A
app pub date -
Jul 27, 2000
filing date -
Jul 28, 1999
priority date (Note) -
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Abstract
The present invention relates to an overlay mark used for the measurement of the overlay accuracy between layered patterns and alignment at the time of exposure; which has a grooved pattern surrounding a mark pattern that is formed by engraving a groove or an indent in a prescribed position on a layer where a circuit pattern is formed so as to protect this mark pattern from being deformed by thermal expansion or contraction of this layer. The present invention enables to form a multi-layered circuit pattern with a high accuracy and a high yield in production, even in the formation of a minute and densely-spaced circuit pattern.
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