Multiple-thread processor with single-thread interface shared among threads
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United States of America Patent
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Oct 5, 2004
Grant Date -
Sep 26, 2002
app pub date -
May 23, 2002
filing date -
May 11, 1999
priority date (Note) -
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Abstract
A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, 'pollution', or 'cross-talk' between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
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