Integrated device package and fabrication methods thereof
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 12, 2004
Issued Date -
N/A
app pub date -
Jul 19, 2001
filing date -
Feb 10, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a in centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality in of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully