Content addressable memory (CAM) devices having CAM array blocks therein that conserve bit line power during staged compare operations
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United States of America Patent
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Oct 12, 2004
Issued Date -
N/A
app pub date -
Apr 9, 2003
filing date -
Apr 10, 2002
priority date (Note) -
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Abstract
Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.
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