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Abstract

A nonvolatile memory apparatus which includes a plurality of terminals including a clock terminal, a command terminal and other terminal, a converter circuit, end a plurality of nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands which include a read command and a program command. In an operation in response to the read command received from the command terminal, the nonvolatile memory apparatus is capable of reading data in parallel from ones of the nonvolatile memory cells, converts parallel type data to serial type data by the converter circuit and serially outputs data via the other terminal not the command terminal in response to the clock signal. Also in an operation in response to the program command, the nonvolatile memory apparatus serially receives data via the other terminal not the command terminal in response to the clock signal, converts serial type data to parallel type data by the converter circuit and is capable of writing data in parallel to ones of the nonvolatile memory cells.

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First Claim