Two step memory device command buffer apparatus and method and memory devices and computer systems using same
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United States of America Patent
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Oct 12, 2004
Issued Date -
N/A
app pub date -
Nov 6, 2002
filing date -
Jun 13, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of four 10-bit command words in each packet. After the first two words of each packet have been stored, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received.
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