Method of manufacturing non-volatile memory device

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United States of America Patent

PATENT NO 6806148
SERIAL NO

10447715

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Abstract

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A method of forming an integrated circuit, includes, in part: forming trench isolation in a semiconductor substrate, forming a first well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric layer above the first oxide layer, forming a first polysilicon gate layer above the first dielectric layer, forming a second dielectric layer above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, and forming a second spacer to define source and drain regions.

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Patent Owner(s)

Patent OwnerAddress
O2IC INC3910 FREEDOM CIRCLE SUITE 103 SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Choi, Kyu Hyun Cupertino, CA 36 465
Li, Sheau-suey Cupertino, CA 11 738

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