Semiconductor input/output circuit arrangement
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United States of America Patent
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Oct 19, 2004
Grant Date -
Jul 24, 2003
app pub date -
Aug 26, 2002
filing date -
Aug 24, 2001
priority date (Note) -
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Abstract
A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.
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