Page-erasable flash memory
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United States of America Patent
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Oct 19, 2004
Grant Date -
Jan 29, 2004
app pub date -
May 15, 2003
filing date -
Nov 15, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.
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