Disconnecting a device on a cache line boundary in response to a write command

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United States of America Patent

PATENT NO 6807590
SERIAL NO

09542157

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Abstract

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Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amount of free space available in the write buffer. When the data in the write buffer approaches the capacity of the write buffer, the system prepares for a potential disconnect of the write initiating device from the bridge device. Data alignment with cache line boundaries is maintained upon disconnect by adjusting the available free space in the write buffer to equal a multiple of a cache line amount of data. The write initiating device is disconnected when the data in the write buffer equals a write buffer full status.

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Patent Owner(s)

Patent OwnerAddress
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP11445 COMPAQ CENTER DRIVE WEST HOUSTON TX 77070

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Callison, Ryan A Spring, TX 38 1610
Carlson, Jeff M Cypress, TX 8 260

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