Integrated circuit device having double data rate capability
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United States of America Patent
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Oct 19, 2004
Issued Date -
N/A
app pub date -
Jan 22, 2002
filing date -
Apr 18, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal. A second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal. In addition, the integrated circuit device includes a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.
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