Importance

Loading Importance Indicators...

Abstract

Simple, glitch-free phase detector circuits provide add and subtract output signals indicating the phase relationship between two input clock signals. Some embodiments also provide a lock output signal having a lock window, and in some of these embodiments, the size of the lock window is programmable. An optionally delayed version of the feedback clock signal is stored a first time when the input clock signal goes high, then stored a second time after a predetermined delay. In some embodiments, the predetermined delay is programmable. When both stored values are low, the subtract output signal is active. When the first stored value is high, the add output signal is active, regardless of the state of the second stored value. When the first stored value is low and the second stored value is high, the two clocks are synchronized and the phase detector indicates a lock condition.

Loading the Abstract Image...

First Claim