Logic simulation method and logic simulation apparatus
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United States of America Patent
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-
Nov 2, 2004
Grant Date -
N/A
app pub date -
Jul 17, 2000
filing date -
Feb 4, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An MWL signal encoding part encodes a signal occurring on a main word signal line, an SD signal encoding part encodes a signal occurring on a subdecode signal line, a WL calculating part calculates a WL value, based on an MWL signal encoded value and an SD signal encoded value; an input and output operation part allows one-word data in a memory cell selected by the WL value to be read and written via the bit signal line; and a read and write control part controls a read operation and a write operation of the input and output operation part, based on a signal level on the bit signal line.
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