Dual-edge fifo interface
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United States of America Patent
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Nov 2, 2004
Issued Date -
N/A
app pub date -
May 12, 2000
filing date -
Jun 17, 1997
priority date (Note) -
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Abstract
A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.
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