Silicon object array with unidirectional segmented bus architecture
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United States of America Patent
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Nov 9, 2004
Grant Date -
Jul 8, 2004
app pub date -
Jan 7, 2003
filing date -
Jan 7, 2003
priority date (Note) -
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Abstract
A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.
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