Method for manufacturing stacked chip package
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 16, 2004
Grant Date -
Jul 3, 2003
app pub date -
Dec 11, 2002
filing date -
Dec 29, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention relates to manufacture of a stacked chip package. A first substrate including a first center window is attached to a first semiconductor chip having a plurality of bonding pads arranged on the center part. A first bonding wire is formed to connect the first semiconductor chip and the first substrate. A second substrate including a second center window is attached to a second semiconductor chip having a plurality of bonding pads arranged on the center part. A second bonding wire is formed to connect the second semiconductor chip end the second substrate. The backsides of the resulting first and the second semiconductor chips are attached. A third bonding wire is formed to connect the first and the second substrates. A molding body is formed to overlay the first, the second and the third bonding wires. A conductive ball is adhered to the first substrate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully