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Abstract

A self-synchronous logic circuit includes scan test compliant registers holding data and forming stages of a pipeline, and scan test compliant self-synchronous signal control circuits corresponding to respective registers and performing handshake to transfer clocks. In accordance with the clocks transferred by the scan test compliant self-synchronous signal control circuits, data processing among the scan test compliant registers proceeds. In addition to normal data processing, the scan test compliant registers have a function of serially transferring contents thereof at the time of a test. The scan test compliant self-synchronous signal control circuits are set to a state that corresponds to the end of a third way of the handshake, at the time of a test.

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First Claim