DSP unit for multi-level global accumulation
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United States of America Patent
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Nov 16, 2004
Grant Date -
Apr 15, 2004
app pub date -
Jul 29, 2003
filing date -
Mar 31, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.
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