SRAM-compatible memory device employing DRAM cells
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United States of America Patent
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Nov 23, 2004
Grant Date -
Mar 4, 2004
app pub date -
Aug 12, 2003
filing date -
Aug 27, 2002
priority date (Note) -
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Abstract
Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh clock signal having a period 'n' times a period of a reference clock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.
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