Exception handling using an exception pipeline in a pipelined processor
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United States of America Patent
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Nov 23, 2004
Grant Date -
Jun 20, 2002
app pub date -
Dec 15, 2000
filing date -
Dec 15, 2000
priority date (Note) -
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Abstract
A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.
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