Programmable memory devices with latching buffer circuit and methods for operating the same
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United States of America Patent
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Nov 30, 2004
Grant Date -
Nov 13, 2003
app pub date -
Mar 31, 2003
filing date -
May 13, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
Programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between the bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node. Methods of operating the same are also provided.
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