Chip size stack package and method of fabricating the same
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United States of America Patent
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Dec 7, 2004
Issued Date -
N/A
app pub date -
Apr 28, 2003
filing date -
Jun 28, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A chip size stack package includes two semiconductor chips arranged such that their bond pads-forming surfaces are opposed and insulating layers are applied thereto. Via-holes for exposing bond pads are formed in the insulating layers. Metal traces exposed at both sides of the insulating layers are formed on the via-holes, whereby the insulating layers are bonded to each other and the metal traces are bonded to each other. Ends of metal wires are connected to the metal traces exposed at the insulating layers, and both sides of the chips are molded by an encapsulate leaving the other ends of the metal wires exposed.
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