Multiple logical interfaces to a shared coprocessor resource
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United States of America Patent
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Dec 7, 2004
Grant Date -
N/A
app pub date -
Sep 6, 2000
filing date -
Sep 6, 2000
priority date (Note) -
Expired
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Abstract
An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
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