Fault tolerant mastership system and method

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United States of America Patent

PATENT NO 6832331
SERIAL NO

09788108

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system for indicating and determining a master unit from a plurality of logic units is described. The system includes a first logic unit configured to output a first obey signal and receive a first input signal, and a second logic unit configured to output a second obey signal and receive a second input signal. At least one of the first obey signal and the second obey signal is clocked, and a phase relationship of the second obey signal relative to the first obey signal is controllable by the first and second input signals. The system also includes a mastership determination logic unit configured to monitor the first and second obey signals. The mastership determination logic unit is configured to indicate that the first logic unit is the master unit when only the first obey signal is being clocked and to indicate that the second logic unit is the master unit when only the second obey signal is being clocked. The mastership determination logic unit is also configured to indicate that the first logic unit is the master unit when the first and second signals are being clocked in-phase and to indicate that the second logic unit is the master unit when the first and second signals are being clocked out-of-phase. A method of similar features is also describe.

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Patent Owner(s)

  • TELICA, INC.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldara, Stephen A Sudbury, MA 45 2087
Garcen, Sean Hudson, MA 4 12
Manning, Thomas A Northborough, MA 40 1980

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