Information processing system with memory modules of a serial bus architecture
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United States of America Patent
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Jan 4, 2005
Grant Date -
Dec 19, 2002
app pub date -
Jun 11, 2002
filing date -
Jun 14, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.
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