Solderless electronics packaging

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6840777
SERIAL NO

09726629

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sathe, Ajit V Chandler, AZ 13 310
Wermer, Paul H San Francisco, CA 12 766

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