Method of making floating gate non-volatile memory cell with low erasing voltage having double layer gate dielectric
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 11, 2005
Issued Date -
N/A
app pub date -
Mar 3, 2004
filing date -
Sep 30, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully