Semiconductor device and method of fabricating semiconductor device with high CMP uniformity and resistance to loss that occurs in dicing
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United States of America Patent
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Jan 11, 2005
Grant Date -
Jul 29, 2004
app pub date -
Nov 19, 2003
filing date -
Jan 29, 2003
priority date (Note) -
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Abstract
In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.
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