Semiconductor wafer with grouped integrated circuit die having inter-die connections for group testing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6844218
APP PUB NO 20030124816A1
SERIAL NO

10055445

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method of forming a plurality of integrated circuit die on a semiconductor wafer (30). The method forms a first integrated circuit die (32.sub.a) in a first area in a fixed position relative to the semiconductor wafer, by forming at least two devices (42.sub.a) in the first area, the at least two devices selected from a group of active and passive devices, and by forming a first metal layer (62) comprising portions connecting to the at least two devices in the first area. The method also forms a second integrated circuit die (32.sub.b) in a second area in a fixed position relative to the semiconductor wafer, the second area separated from the first area by a scribe area (34). The formation of the second integrated circuit die comprises the steps of forming at least two devices (42.sub.b) in the second area, the at least two devices selected from a group of active and passive devices, and forming the first metal layer to further comprise portions connecting to the at least two devices in the second area. The method also forms the first metal layer to further comprise a portion electrically connecting a portion of the first metal layer in the first area to a portion of the first metal layer in the second area and thereby extending in the scribe area.

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Patent Owner(s)

Patent OwnerAddress
TEXAS INSTRUMENTS INCORPORATED12500 TI BOULEVARD MS 3999 DALLAS TX 75243

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Potts, David J Rowlett, TX 2 36

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