Word line driver circuit for a content addressable memory
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United States of America Patent
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Jan 18, 2005
Grant Date -
N/A
app pub date -
Mar 21, 2003
filing date -
Mar 21, 2003
priority date (Note) -
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Abstract
A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operation. For some embodiments, the word line driver circuit selectively provides a relatively high word line read voltage or a relatively low word line read voltage in response to the compare signal.
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