Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register
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United States of America Patent
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Jan 18, 2005
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N/A
app pub date -
Jun 15, 2004
filing date -
Nov 6, 2003
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Abstract
A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.
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