Planar byte memory organization with linear access
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United States of America Patent
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Jan 25, 2005
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N/A
app pub date -
Feb 20, 2002
filing date -
Feb 20, 2001
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Abstract
A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).
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