Floating point divide and square root processor

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United States of America Patent

PATENT NO 6847985
SERIAL NO

09927139

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Abstract

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An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]-S.sub.j+1 *D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, S.sub.j+1 is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]-2S[j]S.sub.j+1, where W[j] is the estimated partial remainder and S.sub.j+1 is the estimated result generated during the current iteration, j. A shift register shifts the value of the estimated result, S.sub.j+1, to generate -S.sub.j+1.sup.2.multidot.2.sup.-(j+1), which is summed with the result from the first summing device to generate the estimated partial remainder for the square root mode.

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Patent Owner(s)

Patent OwnerAddress
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE LTDSINGAPORE SINGAPORE SINGAPORE CITY SINGAPORE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gupta, Gagan V Union City, CA 4 41
Yu, Mengchen Fremont, CA 3 41

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