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Abstract

A memory device includes a memory array, a first protocol circuit, a second protocol circuit, an operation interface, and a protocol detection circuit. The first protocol circuit, which implements a first communication protocol, and the second protocol circuit, which implements a second communication protocol, are coupled in parallel between the memory array and the operation interface. The protocol detection circuit, which is coupled to the operation interface and to the first and second protocol circuits, monitors control signals provided to the operation interface by a host controller to determine which communication protocol the host controller employs. In response thereto, the protocol detection circuit selects one of the first and second protocol circuits to handles communication between the host controller and the memory device.

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First Claim